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femtoclock ? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 8421002I-01 revision b 8/14/15 1 ?2015 integrated device technology, inc. g eneral d escription the 8421002I-01 is a 2 output hstl synthesizer optimized to generate ethernet reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from idt. using a 25mhz, 18pf parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (f_sel[1:0]): 156.25mhz, 125mhz and 62.5mhz. the 8421002I-01 uses idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. the 8421002I-01 is packaged in a small 20-pin tssop package. f eatures ? two hstl outputs (vohmax = 1.5v) ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? supports the following output frequencies: 156.25mhz, 125mhz, 62.5mhz ? vco range: 560mhz - 680mhz ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1.875mhz - 20mhz): 0.44ps (typical) ? power supply modes: core/output 3.3v/1.8v 2.5v/1.8v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) compliant package 11 0 1 0 phase detector vco m = 25 (fixed) f_sel[1:0] 0 0 4 (default) 0 1 5 1 0 10 1 1 not used 2 osc 8421002I-01 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view b lock d iagram output frequency (25mhz ref.) f_sel1 f_sel0 m divider value n divider value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 not used not used f requency s elect f unction t able f_sel[1:0] npll_sel ref_clk xtal_in xtal_out nxtal_sel mr q0 nq0 q1 nq1 pulldown pulldown 25mhz pulldown pulldown pulldown nc v ddo q0 nq0 mr npll_sel nc v dda f_sel0 v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v ddo q1 nq1 gnd v dd nxtal_sel ref_clk xtal_in xtal_out f_sel1 p in a ssignment
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 2 revision b 8/14/15 t able 1. p in d escriptions t able 2. p in c haracteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values.
revision b 8/14/15 8421002I-01 data sheet 3 femtoclocks? crystal-to-hstl frequency synthesizer a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 3a. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 3c. lvcmos / lvttl dc c haracteristics , v dd = v dda = 3.3v5% or 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 3b. p ower s upply dc c haracteristics , v dd = v dda = 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current 110 ma i dda analog supply current 12 ma i ddo output supply current no load 0 ma symbol parameter test conditions minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current 96 ma i dda analog supply current 12 ma i ddo output supply current no load 0 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current ref_clk, mr, f_sel0, f_sel1, npll_sel, nxtal_sel v dd = v in = 3.465v or 2.5v 150 a i il input low current ref_clk, mr, f_sel0, f_sel1, npll_sel, nxtal_sel v dd = 3.465v or 2.5v, v in = 0v -150 a
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 4 revision b 8/14/15 t able 4. c rystal c haracteristics t able 3d. hstl dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 3e. hstl dc c haracteristics , v dd = v dda = 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 1.0 1.5 v v ol output low voltage; note 1 0 0.5 v v ox output crossover voltage; note 2 40 60 % v swing peak-to-peak output voltage swing 0.6 1.3 v note 1: outputs terminated with 50
revision b 8/14/15 8421002I-01 data sheet 5 femtoclocks? crystal-to-hstl frequency synthesizer t able 5a. ac c haracteristics , v dd = v dda = 3.3v5%,v ddo = 1.8v0.2v, t a = -40c to 85c t able 5b. ac c haracteristics , v dd = v dda = 2.5v5%,v ddo = 1.8v0.2v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f out output frequency f_sel[1:0] = 00 140 170 mhz f_sel[1:0] = 01 112 136 mhz f_sel[1:0] = 10 56 68 mhz tsk(o) output skew; note 1, 3 20 ps tjit(?) rms phase jitter (random); note 2 156.25mhz, (1.875mhz - 20mhz) 0.44 ps 125mhz, (1.875mhz - 20mhz) 0.48 ps 62.5mhz,(1.875mhz - 20mhz) 0.49 ps t r / t f output rise/fall time 20% to 80% 215 815 ps odc output duty cycle 48 52 % note 1: de ned as skew between outputs at the same supply voltages and with equal load conditions. measured at v ddo /2. note 2: please refer to the phase noise plot. note 3: this parameter is de ned in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f out output frequency f_sel[1:0] = 00 140 170 mhz f_sel[1:0] = 01 112 136 mhz f_sel[1:0] = 10 56 68 mhz tsk(o) output skew; note 1, 3 20 ps tjit(?) rms phase jitter (random); note 2 156.25mhz, (1.875mhz - 20mhz) 0.41 ps 125mhz, (1.875mhz - 20mhz) 0.49 ps 62.5mhz,(1.875mhz - 20mhz) 0.50 ps t r / t f output rise/fall time 20% to 80% 315 715 ps odc output duty cycle 48 52 % note 1: de ned as skew between outputs at the same supply voltages and with equal load conditions. measured at v ddo /2. note 2 please refer to the phase noise plot. note 3 this parameter is de ned in accordance with jedec standard 65.
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 6 revision b 8/14/15 t ypical p hase n oise at 156.25mh z @ 3.3v 156.25mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.44ps (typical) o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m ethernet jitter filter ? ? ? ? ? ?
revision b 8/14/15 8421002I-01 data sheet 7 femtoclocks? crystal-to-hstl frequency synthesizer p arameter m easurement i nformation o utput s kew hstl 2.5v/1.8v o utput l oad ac t est c ircuit hstl 3.3v/1.8v o utput l oad ac t est c ircuit o utput r ise /f all t ime rms p hase j itter o utput d uty c ycle /p ulse w idth /p eriod
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 8 revision b 8/14/15 c rystal i nput i nterface the 8421002I-01 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below figure 2. c rystal i npu t i nterface were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the 8421002I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10
revision b 8/14/15 8421002I-01 data sheet 9 femtoclocks? crystal-to-hstl frequency synthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the 8421002I-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8421002I-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? ? total power _max (3.465v, with all outputs switching) = 422.7mw + 65.6mw = 488.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = tj = junction temperature pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 10 revision b 8/14/15 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. hstl output driver circuit and termination are shown in figure 3. t o calculate worst case power dissipation into the load, use the following equations which assume a 50
revision b 8/14/15 8421002I-01 data sheet 11 femtoclocks? crystal-to-hstl frequency synthesizer r eliability i nformation t ransistor c ount the transistor count for 8421002I-01 is: 2951 t able 7. 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 12 revision b 8/14/15 p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions symbol millimeters min max n20 a -- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75
revision b 8/14/15 8421002I-01 data sheet 13 femtoclocks? crystal-to-hstl frequency synthesizer t able 9. o rdering i nformation part/order number marking package shipping packaging temperature ics8421002agi-01lf ics1002ai01l 20 lead ?lead-free? tssop tube -40c to 85c ics8421002agi-01lft ics1002ai01l 20 lead ?lead-free? tssop tape & reel -40c to 85c note: parts that are ordered with an ?lf? suf x to the part number are the pb-free con guration and are rohs compliant.
femtoclocks? crystal-to-hstl frequency synthesizer 8421002I-01 data sheet 14 revision b 8/14/15 revision history sheet rev table page description of change date b 3a, 3b 3 power supply tables - corrected v ddo min/max. 8/8/06 b t9 13 ordering information - removed leaded devices. updated data sheet format. 4/6/15 b product discontinuation notice - last time buy expires august 14, 2016 pdn cq-15-04 8/14/15
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